by Playfuls Staff |
16th January 2007
HP announced today that its research department came up with a breakthrough discovery, which could lead to the creation of field programmable gate arrays (FPGAs) up to eight times denser.[more]
The new FPGAs will use less energy for a given computation than those currently being produced.
Moreover, such chips could be built using the same sized transistors as those used in today’s FPGA design. This gives HP’s invention the advantage of making only small modifications to existing fabrication facilities for chip manufacturing.
FPGAs are integrated circuits with programmable logic components and interconnects that can be adapted by end-users for specific applications. They are used in a wide range of industries, including communications, automotive and consumer electronics.
Applications of FPGAs include DSP, software-defined radio, aerospace and defense systems, ASIC prototyping, medical imaging, computer vision, speech recognition, cryptography, bioinformatics, computer hardware emulation and a growing range of other areas. FPGAs originally began as competitors to CPLDs and competed in a similar space, that of glue logic for PCBs. As their size, capabilities, and speed increased, they began to take over larger and larger functions to the state where some are now marketed as full systems on chips (SOC).
FPGAs especially find applications in any area or algorithm that can make use of the massive parallelism offered by their architecture. One such area is code breaking, in particular brute-force attack, of cryptographic algorithms.
The technology calls for a nanoscale crossbar switch structure to be layered on top of conventional CMOS (complementary metal oxide silicon), using an architecture HP Labs researchers have named “field programmable nanowire interconnect (FPNI)” – a variation on the well-established FPGA technology.
The research, by Greg Snider and Stan Williams of HP Labs, is a featured paper in the Jan. 24 issue of Nanotechnology, a publication of the British Institute of Physics (“Nano/CMOS Architectures Using Field-Programmable Nanowire Interconnect,” www.iop.org/journals/nano). The research was conducted using classic modeling and simulation techniques, but Williams said HP is working on producing an actual chip using the approach, and could have a laboratory prototype completed within the year.
“As conventional chip electronics continue to shrink, Moore’s Law is on a collision course with the laws of physics,” said Williams, an HP Senior Fellow and director, Quantum Science Research, HP Labs. “Excessive heating and defective device operation arise at the nanoscale. What we’ve been able to do is combine conventional CMOS technology with nanoscale switching devices in a hybrid circuit to increase effective transistor density, reduce power dissipation, and dramatically improve tolerance to defective devices.”
The work uses a conceptual breakthrough for connecting a crossbar to CMOS by Dmitri Strukov and Konstantin Likharev of Stony Brook University in New York. The HP approach relies on extensive experience in fabricating crossbars and makes a number of changes designed to improve the manufacturability of the circuits.
In the FPNI approach, all logic operations are performed in the CMOS, whereas most of the signal routing in the circuit is handled by a crossbar that sits above the transistor layer. Since conventional FPGAs use 80 to 90 percent of their CMOS for signal routing, the FPNI circuit is much more efficient; the density of transistors actually used for performing logic is much higher and the amount of electrical power required for signal routing is decreased.
The researchers presented a “conservative” chip model using 15-nanometer-wide crossbar wires combined with 45-nm half-pitch CMOS, which they said they believe could be technologically viable by 2010. That would be equivalent to leaping ahead three generations on the International Technology Roadmap for Silicon without having to shrink the transistors, they said.
“The expense of fabricating chips is increasing dramatically with the demands of increasing manufacturing tolerances,” said Snider, senior architect, Quantum Science Research, HP Labs. “We believe this approach could increase the usable device density of FPGAs by a factor of eight, using tolerances that are no greater than those required of today’s devices.”
Snider and Williams also used a model based on 4.5-nm-wide crossbar wires, which they said could be ready by 2020. The 4.5-nm crossbar architecture combined with 45-nm CMOS would yield a hybrid FPGA about 4 percent the size of a 45-nm CMOS-only FPGA. In this case, the clock speed will likely decrease, but so will energy per computation. The opportunity is in the parallelism offered by FPGAs – with lots of parallelism to exploit, this architecture requires much less energy to operate.
Because of the tiny sizes of the nanowires and switches in the crossbars, the researchers said they expected defect rates to be relatively high. However, with the crossbar interconnect it is possible to route around defects, the researchers said. Their simulations showed that an FPNI chip with 20 percent of the nanowires broken in random locations still had an effective production yield of 75 percent and did not present significant performance compromises, which should make it economically feasible to produce.
“This is work that is directed toward solving a problem that we face in the long term,” said Ivo Bolsens, chief technology officer of San Jose chip maker Xilinx, who is familiar with the work of Williams and his team.
Until now, chip makers have achieved performance gains by making the transistors smaller and smaller. But this technique, which had led to the doubling of transistors and performance gains, is running out of steam as the greater density of circuitry generates so much excess heat that it causes performance problems.
Big chip makers such as Intel of Santa Clara and Advanced Micro Devices of Sunnyvale continue to shrink transistors, but they are also now developing multicore chips, with multiple brains on one piece of silicon, to provide a boost in performance.
“A multicore is an admission of failure,” Williams said. HP is a computer and printer maker, but HP Labs does work in a wide range of areas relating to science and computing.
Williams said that if HP can prove its chip design works in manufacturing, this technique could provide a boost to the entire semiconductor industry.
“It's very likely that we will figure out how to make the intention of Moore's Law go on for several more decades instead of running out sometime in the next decade if things get too small,” Williams said.
The Hewlett-Packard Company, commonly known as HP, is currently the world's largest information technology corporation and is known worldwide for its printers and personal computers. Headquartered in Palo Alto, California, United States, it has a global presence in the fields of computing, printing, and digital imaging, and also provides software and services.
HP posted US$91.7 billion in annual revenue in 2006, accelerating the competition with IBM for the distinction of being the world's largest technology vendor in terms of sales. HP is now the No. 1 ranking company in worldwide personal computer shipments, surpassing rival Dell, market research firms Gartner and IDC reported in October 2006.
