by Playfuls Staff |
12th February 2007
Enlisted in the battle for supremacy in the desktop and server markets, Intel recently announced the development of a new processor that packs 80 tiny cores on a single chip. But it will not be available for the general public.[more]
Intel promises that the new processor will consume less energy than most of today’s home appliances and that it will not be larger than a human nail. Intel says that the "teraflops research chip" is the first that can deliver supercomputing-like capabilities.
The 80-core chip is the result of the Intel’s innovative ‘Tera-scale computing’ research aimed at delivering Teraflop- or trillions of calculations per second- performance for future PCs and servers.
Technical details of the Teraflop research chip will be presented at the annual Integrated Solid State Circuits Conference (ISSCC) this week in San Francisco.
First described by Intel executives at a September trade show, the chip fits 80 cores onto a 275-square millimeter, fingernail-size chip and draws only 62 watts of power -- less than many modern desktop chips.
Tera-scale performance, and the ability to move terabytes of data, will play a pivotal role in future computers with ubiquitous access to the Internet by powering new applications for education and collaboration, as well as enabling the rise of high-definition entertainment on PCs, servers and handheld devices. For example, artificial intelligence, instant video communications, photo-realistic games, multimedia data mining and real-time speech recognition – once deemed as science fiction in “Star Trek” shows – could become everyday realities.
A terabyte (derived from the prefix tera-) is a measurement term for data storage capacity equal to 1000 gigabytes (1000.4 or 1024 to be exact), i.e. one trillion (short scale) bytes. IBM's Blue Gene/L is currently the fastest supercomputer in the world. On October 28, 2005 the machine reached 280.6 TFLOPS with 131072 nodes.
"Our researchers have achieved a wonderful and key milestone in terms of being able to drive multi-core and parallel computing performance forward," said Justin R. Rattner, Intel's chief technology officer. "It points the way to the near future when Teraflop-capable designs will be commonplace and will reshape what we can all expect from our computers and the Internet at home and in the office."
Unfortunately, Intel declared firmly that it has no intention to bring their chip exactly how it is designed today (with floating point cores) to the masses. However, the good news is that the Tera-scale research will become an instrument to investigate new innovations in individual or specialized processor or core functions, the types of chip-to-chip and chip-to-computer interconnects required to best move data and most importantly, how software will need to be designed to best leverage multiple processor cores. This Teraflop research chip offered specific insights in new silicon design methodologies, high-bandwidth interconnects and energy management approaches.
The first time Teraflop performance was achieved was in 1996, on the ASCI Red Supercomputer built by Intel for the Sandia National Laboratory. That computer took up more than 2000 square feet, was powered by nearly 10,000 Pentium Pro processors, and consumed over 500 kilowatts of electricity. Intel's research chip achieves this same performance on a multi-core chip that could rest on the tip of a finger.
Also remarkable is that this 80-core research chip achieves a teraflop of performance while consuming only 62 watts - less than many single-core processors today.
Running at 3.16GHz, the new chip achieves 1.01 teraflops of computation -- an efficiency of 16 gigaflops per watt. It can run even faster, but loses efficiency at higher speeds, performing at 1.63 teraflops at 5.1 GHz and 1.81 teraflops at 5.7 GHz.
"If we simply added more than 16 cores, we would get diminishing returns, because the threads and data traffic would not be used properly, so the cores get in the way of each other. It's like having too many cooks in the kitchen," said Jerry Bautista, director of Intel's tera-scale research program.
The chip features an innovative tile design in which smaller cores are replicated as "tiles," making it easier to design a chip with many cores. With Intel's discovery of new and robust materials to build future transistors and no immediate end in sight for Moore's Law, this lays a path to manufacture multi-core processors with billions of transistors more efficiently in the future.
The Teraflop chip also features a mesh-like "network-on-a-chip" architecture allowing super high bandwidth communications between the cores, and capable of moving Terabits of data per second inside the chip. The research also investigated methods to power cores on and off independently, so only the ones needed to complete a task are used, providing more energy efficiency.
Further Tera-scale research will focus on the addition of 3-D stacked memory to the chip as well as developing more sophisticated research prototypes with many general-purpose Intel Architecture-based cores. Today, the Intel Tera-scale Computing Research Program has more than 100 projects underway that explore other architectural, software and system design challenges.
“Our goal is to continue that scaling, to reach a capability of 10 tera-instructions per second by the year 2015,” Shu-ling Garver and Bob Crepps write on Intel’s site.
“The answer to that lies in Moore’s Law. In parallel with our architecture scaling, our process technology has advanced or scaled at a rate predicted by Moore’s Law. If we look ahead to the next decade, we will have the ability to integrate tens of billions of transistors on a single die. The dual-core Intel Itanium processor, code-named ‘Montecito,’ already uses 1.7 billion transistors.”
Another opportunity cited by the two authors for the Tera-scale Era is to improve efficiency through Fine-Grain Power Management.
“Most existing applications are single-threaded, and most threaded applications have a sequential or single-threaded component. For best single-threaded performance, the core that is processing the thread should run at maximum voltage and frequency. By varying the voltage and frequency of individual cores in a multi-core processor as the number of threads varies, high performance and high energy efficiency can be obtained. Fine-grain voltage and frequency can be used to balance performance and energy use.”
Intel is presenting eight other papers at ISSCC, including one which will cover the Intel Core micro-architecture and its use in dual and quad core processors spanning laptops to desktop PCs and servers, using both 65nm and revolutionary 45nm process technologies. Other papers cover such topics as a Radio Frequency Identification (RFID) reader transceiver chip, a low-power cache for mobile applications and a reconfigurable Viterbi accelerator in addition to novel circuits for on-die supply resonance suppression, on-chip phase-noise measurement and adaptive techniques for variations and aging.
International Solid-State Circuits Conference (ISSCC) is a global forum for presentation of advances in solid-state circuits and Systems-on-a-Chip. The Conference offers a unique opportunity for engineers working at the cutting edge of IC design to maintain technical currency, and to network with leading experts.
